Friday, October 26, 2012

CY8C20247-24LKXI chip reverse

CY8C20247-24LKXI chip reverse, chip decryption, chip crack, mcu
code extraction, mcu crack, mcu reverse.
■ QuietZone? Controller
 Patented Capacitive Sigma Delta PLUS (CSD PLUS?)
sensing algorithm for robust performance
 High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
 Ideal for proximity solutions
 Overlay thickness of 15 mm for glass and 5 mm plastic
 Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
 Reliable and robust touch performance in noisy environments
 Standardized user modules for overcoming noise
■ Low power CapSense

 block with SmartSense? auto-tuning
 Supports a combination of up to 31 buttons or 6 sliders,

proximity sensors
 Low average power consumption - 28 ?A for each sensor at
runtime (wake from sleep and scan sensors every 125 ms)
 SmartSense auto-tuning
 Sets and maintains optimal sensor performance during
 Eliminates system tuning during development and production
 Compensates for variations in manufacturing process
■ Driven shield available on five GPIO pins
 Max load of 100 pF at 3 MHz
 Frequency range: 375 kHz to 3 MHz
 Delivers best-in class water tolerant designs
 Robust proximity sensing in the presence of metal objects
■ Powerful Harvard-architecture processor
 M8C CPU with a maximum speed of 24 MHz
 Operating range: 1.71 V to 5.5 V
 Standby mode: 1.1 μA (typ)
 Deep sleep: 0.1 μA (typ)
 Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
 8 KB flash, 1 KB SRAM
 16 KB flash, 2 KB SRAM
 32 KB flash, 2 KB SRAM
 50,000 flash erase/write cycles
 In-system programming capability
■ Four clock sources
 Internal main oscillator (IMO): 6/12/24 MHz
 Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
 RC crystal oscillator
 Clock input
■ Programmable pin configurations
 Up to 32 general-purpose I/Os (GPIOs)
 Dual mode GPIO
 High sink current of 25 mA for each GPIO. Total 120 mA
maximum sink current per chip
 5 mA source current on port 0 and 1 and 1 mA on port 2,3
and 4
 Configurable internal pull-up, high-Z, and open drain modes
 Selectable, regulated digital I/O on port 1
 Configurable input threshold on port 1
■ Versatile analog mux
 Common internal analog bus
 Simultaneous connection of I/O
 High power supply rejection ratio (PSRR) comparator
 Low-dropout voltage regulator for all analog resources
■ Additional system resources
 I2C slave:
 Selectable to 50 kHz, 100 kHz, or 400 kHz
 Selectable clock stretch or forced Nack mode
 Implementation during sleep modes with less than 100 μA
 I2C wake from sleep with hardware address validation
 12 MHz SPI master and slave
 Three 16-bit timers
 Watchdog and sleep timers
 Internal voltage reference
 Integrated supervisory circuit
 10-bit incremental analog-to-digital converter (ADC)
 Two general-purpose high speed, low power analog comparators
■ Complete development tools
 Free development tool (PSoC Designer?)
■ Package options
 16-pin SOIC (150 mil)
 16-pin QFN – 3 × 3 × 0.6 mm
 24-pin QFN – 4 × 4 × 0.6 mm
 32-pin QFN – 5 × 5 × 0.6 mm
 48-pin QFN – 6 × 6 × 0.6 mm
 30-ball WLCSP

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