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The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■ The Core
■ CapSense Analog System
■ System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
Each CY8C20X36A/46A/66A/96A/46AS/66AS PSoC device
includes a dedicated CapSense block that provides sensing and
scanning control circuitry for capacitive sensing applications.
Depending on the PSoC package, up to 36 GPIO are also
included. The GPIO provides access to the MCU and analog